Integrated circuit (IC) designers commonly describe their designs in hardware description language (HDL) such as Verilog, VHDL, SystemC, and the like. In IC design, hardware emulation may refer to the process of replicating behavior of one or more pieces of hardware such as a circuit design, hereinafter also referred to as a design under test (DUT), with another piece of hardware, such as a special-purpose emulation system. An emulation model is usually generated in accordance with an HDL source code representing the design under test. The emulation model is compiled into a format used to program the emulation system that may include one or more field programmable gate array (FPGA). Thereby, the DUT is mapped by the compiler into the FPGA(s) of the emulation system. Running the emulation system as programmed with the emulation model enables debugging and functional verification of the DUT. Overall progress of the emulation is usually controlled by a master clock signal generated on the emulator hardware, which enables the emulation model to run on the emulation hardware at much higher speed than when simulating the DUT entirely in software.
Conventional methods to correct for FPGA compiler failures in an FPGA-based emulation system may be resource intensive and failures may take weeks or months to correct. Additionally, changes to the original circuit design or a change in setup (for example, changes in debug parameters) may cause instability in the FPGA compilation due to the presence of tangled logic (defined below). Thus, there is the need for a fully automated solution to detect tangled logic and to take advantage of the partitioning of the detected tangled logic to ensure success of and reduce resource allocation during the FPGA compilation.